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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">PMCNTEN, Performance Monitors Count Enable register</h1><p>The PMCNTEN characteristics are:</p><h2>Purpose</h2>
        <p>Enables the Cycle Count Register, PMU.PMCCNTR_EL0, and any implemented event counters <a href="AArch32-pmevcntrn.html">PMEVCNTR&lt;n&gt;</a>.</p>
      <h2>Configuration</h2><p>External register PMCNTEN bits [63:0] are architecturally mapped to AArch64 System register <a href="AArch64-pmcntenset_el0.html">PMCNTENSET_EL0[63:0]</a>.</p><p>External register PMCNTEN bits [63:0] are architecturally mapped to AArch64 System register <a href="AArch64-pmcntenclr_el0.html">PMCNTENCLR_EL0[63:0]</a>.</p><p>External register PMCNTEN bits [31:0] are architecturally mapped to AArch32 System register <a href="AArch32-pmcntenset.html">PMCNTENSET[31:0]</a>.</p><p>External register PMCNTEN bits [31:0] are architecturally mapped to AArch32 System register <a href="AArch32-pmcntenclr.html">PMCNTENCLR[31:0]</a>.</p><p>This register is present only when FEAT_PMUv3_EXT64 is implemented. Otherwise, direct accesses to PMCNTEN are <span class="arm-defined-word">RES0</span>.</p><h2>Attributes</h2>
        <p>PMCNTEN is a 64-bit register.</p>
      <p>This  register is part of the <a href="pmu.html">PMU</a> block.</p><h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>63</td><td>62</td><td>61</td><td>60</td><td>59</td><td>58</td><td>57</td><td>56</td><td>55</td><td>54</td><td>53</td><td>52</td><td>51</td><td>50</td><td>49</td><td>48</td><td>47</td><td>46</td><td>45</td><td>44</td><td>43</td><td>42</td><td>41</td><td>40</td><td>39</td><td>38</td><td>37</td><td>36</td><td>35</td><td>34</td><td>33</td><td>32</td></tr></thead><tfoot><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></tfoot><tbody><tr class="firstrow"><td class="lr" colspan="31"><a href="#fieldset_0-63_33">RES0</a></td><td class="lr" colspan="1"><a href="#fieldset_0-32_32-1">F0</a></td></tr><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_31">C</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P30</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P29</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P28</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P27</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P26</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P25</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P24</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P23</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P22</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P21</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P20</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P19</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P18</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P17</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P16</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P15</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P14</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P13</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P12</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P11</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P10</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P9</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P8</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-30_0">P0</a></td></tr></tbody></table><h4 id="fieldset_0-63_33">Bits [63:33]</h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-32_32-1">F0, bit [32]<span class="condition"><br/>When FEAT_PMUv3_ICNTR is implemented:
                        </span></h4><div class="field">
      <p>PMU.PMICNTR_EL0 counter enable. Enables the instruction counter.</p>
    <table class="valuetable"><tr><th>F0</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PMU.PMICNTR_EL0 disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>PMU.PMICNTR_EL0 enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-32_32-2"><span class="condition"><br/>Otherwise:
                        </span></h4><div class="field">
      <p>Reserved, <span class="arm-defined-word">RES0</span>.</p>
    </div><h4 id="fieldset_0-31_31">C, bit [31]</h4><div class="field">
      <p>PMU.PMCCNTR_EL0 enable. Enables the cycle counter register. Possible values are:</p>
    <table class="valuetable"><tr><th>C</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PMU.PMCCNTR_EL0 is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>PMU.PMCCNTR_EL0 enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><h4 id="fieldset_0-30_0">P&lt;n&gt;, bit [n], for n = 30 to 0</h4><div class="field"><p>Event counter enable for PMU.PMEVCNTR&lt;n&gt;_EL0.</p>
<p>If PMU.PMCFGR.N is less than 31, bits [30:PMU.PMCFGR.N] are RAZ/WI.</p><table class="valuetable"><tr><th>P&lt;n&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>PMU.PMEVCNTR&lt;n&gt;_EL0 is disabled.</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>PMU.PMEVCNTR&lt;n&gt;_EL0 is enabled.</p>
        </td></tr></table><p>The reset behavior of this field is:</p><ul><li>On a Warm reset, 
      this field resets
       to an architecturally <span class="arm-defined-word">UNKNOWN</span> value.</li></ul></div><div class="access_mechanisms"><h2>Accessing PMCNTEN</h2><p>Accesses to this register use the following encodings:</p><h4 class="assembler">Accessible at offset 0xC10 from PMU</h4><ul><li>When DoubleLockStatus(), or !IsCorePowered(), or OSLockStatus() or !AllowExternalPMUAccess(), accesses to this register generate an error response.
          </li><li>Otherwise, accesses to this register are <span class="access_level">RW</span>.
          </li></ul><table class="access_instructions"><tr/><tr/></table></div><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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